The present invention relates to the field of semiconductor memory devices, and, more particularly, to circuits for the selection of memory rows during high speed read operations.
In semiconductor memory devices there are circuits for selecting and deselecting addressed memory cells. In general, these circuits are as illustrated in FIG. 1 and include a pair of functional blocks, namely ROW_DECODING and COL_DECODING, which stimulate respectively a certain row and a certain column of the memory matrix, corresponding to an externally provided address. The following description will refer to FLASH memories, however, the present invention may also be satisfactorily used in any type of non-volatile memory device.
The reading of data stored in the cells of a FLASH memory is performed by the SENSING block, that measures the current that circulates in the selected cells. If this current exceeds a certain value, the cell is regarded as non-programmed (not written) otherwise it is regarded as programmed (written). To correctly carry out the reading operations in a correctly carry out the reading operations in a sequential manner, the transient currents caused by a preceding selection of a memory row should disappear before selection of a different memory row is initiated.
A particular mode of memory access, known as a fast reading process, includes driving the selection of a new memory row when the previously selected row has not yet been deselected. This mode of memory access that allows for the selection of a memory row while the transients of the previously selected row are not yet decayed allows for a relevant saving of time and therefore an increment of the speed of the device though considerably increasing the risk or erroneous readings of stored bits.
In FLASH memory devices, the reading of stored bits is carried out by measuring the current that flows through the selected cells. If the current through a cell exceeds a pre-established value, the cell is read as not programmed or otherwise as programmed. During a fast reading process, at the start of a new selection, the memory word line (physically connected to the gates of the memory cells of the selected row) relative to the preceding reading may not yet be completely deselected. Therefore, if the new reading operation is carried out while there is still a transient current flowing through a deselected cell (bitline), the SENSING circuit would sense such a current contribution and could erroneously recognize a programmed cell as a non programmed one.
In other words, the fast reading process may involve the risk of the SENSING block being influenced by transient current still flowing in the cell of the row that had been previously selected, beside the current that circulates in the currently selected cell, thus producing erroneous readings.
To better explain this problem related to fast reading processes, a typical case in which a programmed FLASH cell may be erroneously read as a non-programmed cell will be discussed below. A typical time diagram of the main signals involved in a fast reading process is depicted in FIG. 2. During a first reading phase of the X row of the memory (FIRST READING), driven by the logic signal SELECT_ROW_X, the enabling voltage of the memory row ROW_X_(V) increases up to a certain value. Simultaneously, the current circulating through the cells of the selected ROW_X_(I) increases up to a certain value, which is eventually sensed when the logic signal SENSING_X is enabled, thus identifying for example the X cell of the row as a non-programmed cell.
When SELECT_ROW_X switches low, the X row is deselected. However, as it may be noticed, owing to the transients existing in the selection/deselection circuit, the voltage ROW_X_(V) of the deselected memory row X does not reach the zero value immediately but has a certain decay time. During part of this interval, the cells of the X row may remain enabled, implying the existence of a current ROW_X_(I) even if the signal SELECT_ROW_X is low, and such a current contribution may cause an erroneous subsequent reading (SECOND READING). In fact, the subsequently addressed memory row is enabled by the pulse SELECT_ROW_Y switching high when SELECT_ROW_X switch low (i.e. a fast reading is being performed), then when the sensing logic signal SENSING_Y is enabled, an OVERLAP_X+Y_(I) current is perceived whose value equals the sum of the contributions of the deselected ROW_X_(I) and of the current ROW_Y_(I) flowing in the selected cell of row Y.
Hence, such a sum of currents will be different from the contemplated current ROW_Y_(I) (which in the present example is null) thus causing the selected cell of row Y to be sensed as a non-programmed cell. This inconvenience requires a substantially complete decay of the deselection transients before proceeding to the selection and reading on a different word line, thus practically jeopardizing the speed advantages of a fast reading process.
Therefore, a fast deselection of word lines becomes an indispensable requisite in order to reduce the access time of the memory. It is therefore evident that a circuit capable of minimizing the duration of deselection transients on the word line of a nonvolatile FLASH memory to avoid erroneous readings during a fast reading process is desired. Moreover, the approach to the above discussed deselection problem should not penalize the selection time and be implemented with a limited number of additional components for an attendant requisite of minimizing silicon area requirements.
In view of the above, the present invention provides a circuit capable of overcoming the row deselection problem during a fast reading process without increasing selection time nor the occupied silicon area.
More precisely, a feature of the invention is a row selection/deselection circuit for a nonvolatile memory including a decoding line connected between a supply voltage and ground composed of a series of decoding transistors of the same type of conductivity controlled by respective selection signals and at least a load transistor of opposite type of conductivity connected in series to the decoding transistors and biased by a control voltage, having a current terminal coupled to the supply voltage and the other current terminal connected to the last one of the series of decoding transistors, onto which an activating or deactivating voltage signal of a word line of the memory array is produced.
The circuit of the invention further comprises a circuit for controlling the load transistor including a sensing element in series with the decoding transistors and the load transistor producing a sensing signal switching between a first level when only one memory word line is selected and a second level when more than one memory word line is selected, an inverter input with the sensing signal and outputting a first signal, and a high pass filter input with the first signal and producing a transient control voltage suitable to bring transitorily the load transistor to a state of full conduction when the sensing signal switches from the first to the second level.